Autodetection of a pci express device operating at a wireless rf mitigation frequency

ABSTRACT

A computer system that detects for a PCI Express compliant endpoint device is described. Specifically, the computer system clocks transmit and receive circuits at a first frequency and initiates a training sequence. If the endpoint device successfully trains at the first frequency, the endpoint device is PCI Express compliant. Otherwise, the computer system initiates another training sequence at a second frequency.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a Continuation of U.S. patent application Ser. No.11/026,968, filed on Dec. 29, 2004, and entitled “AUTODETECTION OF A PCIEXPRESS DEVICE OPERATING AT A WIRELESS RF MITIGATION FREQUENCY”. Thisapplication is incorporated herein by reference in its entirety.

FIELD

The present invention pertains to the field of computer system design.More particularly, the present invention relates to a root port thatdetects whether an attached device is operating at a PCI Expressfrequency or an alternative wireless extension frequency.

BACKGROUND

Peripheral Component Interconnect (PCI) is a computer bus designstandard for connecting peripheral components to computers. A PCI bustypically routes signals between a central processing unit (CPU),various other chips on the motherboard, and cards that are plugged intoPCI bus slot connectors. The PCI bus, however, is independent of the CPUchip implemented in a computer system. Thus, the PCI bus is adapted foruse in many different kinds of computers or other high-tech hardware.Earlier versions of the PCI standard included PCI 2.2 and PCI-X.

PCI Express is the third generation of PCI architecture. PCI Expressoffers higher input/output (I/O) bandwidth than its predecessors.Traditional PCI attributes, such as its usage model and softwareinterfaces, are maintained. However, the previous parallel busimplementation has been replaced by a link-to-link serial interface.Further, a split-transaction protocol is implemented with attributedpackets that are prioritized and optimally delivered to their target.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an embodiment of a computer system that supports both PCIExpress compliant devices and non-PCI Express compliant devices.

FIG. 2 is an embodiment of a flowchart to auto-detect a non-PCI Expresscompliant wireless extension device.

FIG. 3 is a block diagram of an embodiment of a device for detecting PCIExpress compliant and non-PCI compliant devices.

DETAILED DESCRIPTION

In the following detailed description, numerous specific details are setforth in order to provide a thorough understanding of the invention.However, it will be understood by those skilled in the art that thepresent invention may be practiced without these specific details. Inother instances, well-known methods, procedures, components and circuitshave not been described in detail so as not to obscure the presentinvention.

The PCI Express architecture is typically composed of a plurality oflayers. For example, a software layer generates PCI Express read andwrite requests. A transaction layer, coupled to the software layer,transports the software-generated requests to I/O devices using apacket-based, split-transaction protocol. A link layer coupled to thetransaction layer adds sequence numbers and a cyclical redundancy check(CRC) number to the packets to create a highly reliable data transfermechanism. Finally, a physical layer coupled to the link layertransports the packets to another PCI Express device.

The PCI Express 1.0a specification supports a frequency of 2.5 gigahertz(GHz). This frequency may be referred to as the Gen1 frequency. The Gen1frequency is similar to the wireless 2.4 GHz spectrum. As a result, theGen1 frequency potentially causes radio frequency (RF) interference withwireless communications.

To reduce the RF interference of a wireless endpoint, a mechanism in aPCI Express port may reduce the data transfer rate. As an example, thedata transfer rate is reduced to 833 megahertz (MHz), or one-third theGen1 frequency. A mechanism to reduce the data transfer rate isdescribed in more detail in co-pending application with Ser. No.10/629,967 entitled, “RF Interference Mitigation by Spectral ShapingUsing Adaptive Data Rate Adjustment for PCI Express Interconnect.” The833 MHz transfer rate is also known as the wireless extension frequency.

By definition of the PCI Express 1.0a specification, a computer systemthat communicates only with a device that operates at the wirelessextension frequency is not PCI Express compliant. To maintain PCIExpress compliance, a computer system that is able to communicate withnon-PCI Express compliant devices also communicates with PCI Expresscompliant devices.

FIG. 1 depicts a PCI Express compliant computer system that is able tocommunicate with both a device operating at the Gen1 frequency and adevice operating at the wireless extension frequency. The computersystem 100 of FIG. 1 comprises a processor 110, a chipset 120, and amemory 150. Computer system 100, which refers to processor 110, chipset120, and memory 150, is coupled to device 160. However, a computersystem may include device 160.

In one embodiment, device 160 is either a PCI Express compliant ornon-PCI Express compliant device. Coupling of device 160 to chipset 120may comprise physically coupling device 160 to chipset 120 or wirelesslycoupling device 160 to chipset 120. As an example, chipset 120 has atransmitter to transmit data to and a receiver to receive data fromcoupled device 160. Device 160, as illustrated, further comprises port170, which is discussed in more detail below.

Chipset 120 is coupled to processor 110, memory 150, and device 160.Chipset 120 is illustrated as a single block; however, chipset 120 isnot so limited. In fact, often chipset 120 comprises a plurality ofcontroller hubs or integrated circuits. As a specific example, chipset120 comprises a memory controller hub (MCH) coupled to processor 110 andmemory 150, as well as a interconnect controller hub (ICH), alsoreferred to as an input/output hub (IOH), coupled to the MCH and I/Odevices through a bus, such as PCI Express. Using typical memory busprotocols, chipset 120 delivers data between the processor 110 andmemory 150.

Also shown in chipset 120 is PCI Express switch 130. In one embodiment,PCI Express switch 130 adjusts a frequency of the data transmitted by atransmitter present in chipset 120. Moreover, the PCI Express switch 130may adjust the clock frequency of its receiver. For example, the switch130 adjusts the receiver clock from the Gen1 frequency to the wirelessextension frequency.

In one embodiment, root port 140, also illustrated in chipset 120,attempts to establish communication with a connected device at the Gen1frequency. If the communication is unsuccessful after N attempts, rootport 140 auto-detects for a connected device operating at a wirelessextension frequency. The root port 140 and PCI Express switch 130 may bepart of the physical layer or any other layer present in a PCI Expressbus/protocol.

FIG. 2 depicts a flowchart of an algorithm for auto-detecting aconnected device operating at a wireless extension frequency. In oneembodiment, the algorithm is implemented by root port 140. As statedabove root port 140 is illustrated in chipset 120; however, root port140 is not so limited, as root port 140 may also be present in aseparate controller hub, integrated circuit, switch, or bridge in thehierarchical connection of a peripheral bus.

In operation 210, root port 140 attempts to “train” a connected endpointdevice at a first frequency. In a first embodiment, data is transmittedat a first frequency. As another example, in addition to transmittingdata at the first frequency, the root port receiver is also clocked atthe first frequency. As a specific example, the first frequency is theGen1 frequency. Training may comprise a “bit-lock” and a “K-align lock”of the physical layers of each device. However training is not solimited. For example, training may also comprises exchanging trainingsequences. Bit-lock refers to the ability of the receiver to properlylock onto specific bits within a bit-stream by identifying bittransition edges. K-align lock refers to the ability of the receiver todetermine symbol boundaries within a bit pattern.

If root port 140 is able to train the endpoint device within X attemptsin operation 220, the endpoint device is PCI Express compliant and thelink negotiation is terminated in operation 270. The number of attempts,X, may be a software programmable value with a hardware default.Furthermore, X may be an integer greater than or equal to one.

However, if root port 140 is unable to train the endpoint device withinX attempts, the receiver is clocked at a second frequency in operation230. The receiver then attempts to K-align at the second frequency. As aspecific example, root port 140 continues to transport/transmit data atthe first frequency. The receiver may attempt to K-align at the secondfrequency for Y attempts in operation 240. The number of attempts, Y,may be a software programmable value with a hardware default, as well asan integer equal to or greater than one. Both the number of attempts Xand Y may also be a predetermined number of attempts in hardware or insoftware, as well as any combination of hardware and software.

Yet, if the receiver fails to K-align at the second frequency inoperation 240, the root port 140 returns to operation 210 and againattempts to train the endpoint device at the first frequency.

On the other hand, if the receiver successfully K-aligns at the secondfrequency, the transmitter is adjusted to transmit data at the secondfrequency in operation 250. Root port 140 next attempts to train theendpoint device within Z attempts at the second frequency in operation260. Thus, the receiver attempts to bit-lock, i.e. properly lock, ontospecific bits within a bit-stream, and to K-align lock to determinesymbol boundaries within a bit pattern. As stated above for X and Y, Zmay also be a predetermined or programmable integer implemented inhardware, software, or firmware.

Nevertheless, if the receiver fails to train the endpoint device at thesecond frequency within Z attempts in operation 260, the root port 140returns to operation 210 and again attempts to train the endpoint deviceat the first frequency. Otherwise, if the receiver successfully trainsat the second frequency within Z attempts, the link negotiation isterminated in operation 270.

FIG. 3 depicts a block diagram of an embodiment of a device fordetecting PCI Express compliant and non-PCI compliant devices. FIG. 3comprises a wireless extension state machine 305, a receive circuitinterface 310, a receive physical interface 320, a clock divider 330, amultiplexer 335, a link training and status state machine 340, atransmit circuit interface 350, a transmit physical layer 360, a phaselocked loop 365, a clock divider 370, and a multiplexer 375.

Receive circuit interface 310 is coupled to receive physical layer 320,clock divider 330, and multiplexer 335. Clock divider 330 is coupled tomultiplexer 335. Receive physical layer 320 is coupled to link trainingand status state machine 340. Link training and status state machine 340and multiplexer 335 are coupled to wireless extension state machine 305.Phase locked loop 365 is coupled to clock divider 370. Clock divider 370is coupled to multiplexer 375. Multiplexer 375 is coupled to linktraining and status state machine 340.

In one embodiment, receive circuit interface 310 receives a signal froma wireless extension endpoint. In another embodiment, receive circuitinterface 310 receives a signal from a PCI Express endpoint. Receivecircuit interface 310 may comprise an I/O buffer. The signal input toreceive circuit interface 310 may comprise a clock and a data signal. Inone embodiment the clock signal is extracted from the data signal.Receive circuit interface 310 may extract the clock from the signal andtransmit the clock to clock divider 330 and multiplexer 335. Receivecircuit interface 310 transmits the data to receive physical layer 320for processing. The data is subsequently passed from the receivephysical layer 320 to link training and status state machine 340 and tothe link layer.

The clock extracted from the signal received by the endpoint device mayhave a Gen1 frequency. As a specific example, clock divider 330 dividesthe clock by three. Thus, the inputs to the multiplexer 335 may be aGen1 frequency and a wireless extension frequency. The wirelessextension state machine 305 transfers a signal to the multiplexer 335 toselect whether the Gen1 frequency or the wireless extension frequency isoutput from the multiplexer 335. For one embodiment, the wirelessextension state machine 305 selects the Gen1 frequency, if the wirelessextension state machine 305 determines that a PCI Express device iscoupled to the receive circuit interface 310 and the transmit circuitinterface 350. However, the wireless extension frequency may be selectedby the wireless extension state machine 305, if the wireless extensionstate machine 305 determines that a wireless extension device is coupledto the receive circuit interface 310 and the transmit circuit interface350.

Besides selecting the receiver clock, in one embodiment, the wirelessextension state machine 305 also selects the transmitter clock. It isapparent that another state machine may select the transmitter clock.Wireless extension state machine 305 provides a select signal tomultiplexer 375. Multiplexer 375 receives a first clock and a secondclock as inputs. A clock having a Gen1 frequency may be generated byphase locked loop 365. The clock having a Gen1 frequency is provided tothe first input of multiplexer 375. The second input to multiplexer 375is provided by the output of clock divider 370. Consequently, in aspecific embodiment, the two inputs to multiplexer 335 are the Gen1frequency and the wireless extension frequency, the Gen1 frequencygenerated by a PLL and the wireless extension frequency being based onthe Gen1 frequency, i.e. the Gen1 frequency divided by 3.

In another embodiment, the wireless extension state machine 305initially selects the Gen1 frequency for both the receiver and thetransmitter clocks. However, the wireless extension frequency or otherfrequency may be selected as the default for the receive andtransmitter, as well as selecting the receiver and transmitter clocksindividually. Receive physical layer 320 receives a clock having a Gen1frequency. Receive physical layer 320 also receives data from receivecircuit interface 310. The data is passed to link training and statusstate machine 340 at the selected frequency rate.

Similarly, transmit physical layer 360 receives a clock having a Gen1frequency. Data is transmitted from the link layer to the physicallayer, which may include status state machine 340. Moreover, data istransmitted to the endpoint device at the Gen1 frequency. As an example,data transmitted to the endpoint device is generated by the link layer.Transmit circuit interface 350 may comprise an I/O buffer to transmitthe data to the endpoint device.

After receiving data from the endpoint device, receive physical layer320 and link training and status state machine 340 attempt to train theendpoint device at the Gen1 frequency. Training is initiated by linktraining and status state machine 340. If the receive physical layer 320and link training and status state machine 340 are successful intraining the endpoint device at the Gen1 frequency, the link trainingand status state machine 340 provides a signal to the wireless extensionstate machine 305 to let the wireless extension state machine 305 knowthat the endpoint device is PCI Express compliant. As a result, wirelessextension state machine 305 will continue to select clocks having Gen1frequencies for multiplexers 335 and 375.

However, if receive physical layer 320 and link training and statusstate machine 340 fail to train the endpoint device at the Gen1 rate,wireless extension state machine 305 may select the wireless extensionclock input for multiplexer 335. Receive physical layer 320 and linktraining and status state machine 340 may then attempt to K-align thedata. For example, receive physical layer 320 may determine symbolboundaries within the bit pattern by looking for a COM symbol. The COMsymbol may be a unique K-code character within a bit-sequence. Ifreceive physical layer 320 and link training and status state machine340 successfully K-align the data, the link training and status statemachine 340 may select the wireless extension clock for multiplexer 375and attempt to train the endpoint device at the wireless extension rate.

In the foregoing specification the invention has been described withreference to specific exemplary embodiments thereof. It will, however,be evident that various modification and changes may be made theretowithout departure from the broader spirit and scope of the invention asset forth in the appended claims. The specification and drawings are,accordingly, to be regarded in an illustrative rather than restrictivesense.

1. An apparatus, comprising: a receive circuit interface adapted toreceive data from an endpoint device; a transmit circuit interfaceadapted to transmit data to the endpoint device based on a transmitinterface clock signal; a receive physical layer coupled to the receivecircuit interface, the receive physical layer adapted to look for bitpatterns in the data received by the receive circuit interface based ona receive interface clock signal; link training logic coupled to thereceive physical layer, the link training logic adapted to detect if theendpoint device is a first endpoint device operating at a firstfrequency or a second endpoint device operating at a second frequency;and wireless extension logic coupled to the link training logic, thewireless extension logic adapted to select either the first or thesecond frequency independently for the receive interface clock signaland the transmit interface clock signal.
 2. The apparatus of claim 1,wherein the link training logic adapted to detect if the endpoint deviceis a first endpoint device operating at a first frequency or a secondendpoint device operating at a second frequency comprises: detecting theendpoint device is a first endpoint device operating at a firstfrequency in response to the receive physical layer successfully findingthe bit patterns in the data received by the receive circuit interfacewhen wireless extension logic selects the first frequency for thereceive interface clock signal; and detecting the endpoint device is asecond endpoint device operating at a second frequency in response tothe receive physical layer successfully finding the bit patterns in thedata received by the receive circuit interface when wireless extensionlogic selects the second frequency for the receive interface clocksignal.
 3. The apparatus of claim 1, wherein the first endpoint deviceis PCI Express compliant and the second endpoint device is a wirelessextension device that is not PCI Express compliant.
 4. The apparatus ofclaim 1, wherein the wireless extension logic is adapted to select thefirst frequency for the receive interface clock signal by default, thereceive physical layer is adapted to look for bit patterns in the datareceived by the receive circuit interface based on the receive interfaceclock signal being at the first frequency in response to the wirelessextension logic selecting the first frequency for the receive interfaceclock signal by default, and the link training logic detecting theendpoint device is a first endpoint device operating at the firstfrequency in response to the receive physical layer indicating the bitpatterns are found at the first frequency.
 5. The apparatus of claim 4,wherein the wireless extension logic is adapted to select the secondfrequency for the receive interface clock signal in response to thereceive physical layer indicating the bit patterns are not found at thefirst frequency after N attempts, the receive physical layer is adaptedto look for bit patterns in the data received by the receive circuitinterface based on the receive interface clock signal being at thesecond frequency in response to the wireless extension logic selectingthe second frequency, and the link training logic detecting the endpointdevice is a second endpoint device operating at the second frequency inresponse to the receive physical layer indicating the bit patterns arefound at the second frequency.